Emitter coupled logic is very fast but uses a lot of power.
2.
The hardware implementation of the HEP PEM was emitter coupled logic.
3.
A differential amplifier is used as the input stage emitter coupled logic gates and as switch.
4.
FASTBUS uses the Emitter coupled logic ( ECL ) electrical standard, which allows higher speed than TTL and generates less switching noise.
5.
The VAX 8600 had a CPU with an 80 ns cycle time ( 12.5 MHz ) implemented with emitter coupled logic ( ECL ) macrocell arrays ( MCAs ).
6.
The Skyline series is powered by Advanced CMOS-ECL ( ACE ), a Hitachi-developed technology that combines the high-density packaging of complementary metal oxide semiconductor ( CMOS ) and the speed of emitter coupled logic ( ECL ) on the same chip.
7.
The Ultra Port Architecture ( UPA ) signals are compatible with 3.3 V Low Voltage Transistor Transistor Logic ( LVTTL ) levels with the exception of differential clock signals which are compatible with 3.3 V pseudo emitter coupled logic ( PECL ) levels.
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