The Weitek FPUs were replaced by a floating point chipset made by Bipolar Integrated Technology and a redesigned vector processor with 32 64-bit vector elements, 8 64-bit scalar floating point registers, 8 32-bit integer registers, and 8 32-bit address registers.
12.
Digital considered using a combined register file, but a split register file was determined to be better as it enabled two-chip implementations to have a register file located on each chip and integer-only implementations to omit the floating-point register file containing the floating point registers.
13.
It had two copies of the integer register file and two copies of floating point register that locate in its front end ( future and scaled file, each contain 2 read and 2 write port . ), and took an extra cycle to propagate data between the two during context switch.
14.
The 8087 automatically converts numbers to this format when loading floating point registers from instructions which transfer values between these internal registers and memory without performing any conversion, which therefore enables access to the extended format for calculations-also reviving the issue of the accuracy of functions of such numbers, but at a higher precision.
15.
Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating point registers are 80 bits wide, the upper 16 bits of the floating point registers are unused in MMX . These bits are set to all ones by any MMX instruction, which correspond to the floating point representation of NaNs or infinities.
16.
Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating point registers are 80 bits wide, the upper 16 bits of the floating point registers are unused in MMX . These bits are set to all ones by any MMX instruction, which correspond to the floating point representation of NaNs or infinities.
17.
In later x86 implementations, like Nehalem and later processors, both integer and floating point registers are now incorporated into a unified octa-ported ( six read and two write ) general-purpose register file ( 8 + 8 in 32-bit and 16 + 16 in x64 per file ), while the register file extended to 2 with enhanced " Shadow Register File Architecture " in favorite of executing hyper threading and each thread uses independent register files for its decoder.
18.
The SPARC uses " Shadow Register File Architecture " as well for its high end line, It had up to 4 copies of integer register files ( future, retirered, scaled, scratched, each contain 7 read 4 write port ) and 2 copies of floating point register file . but unlike Alpha and x86, they are locate in back end as retire unit right after its Out of Order Unit and renaming register files and do not load instruction during instruction fetch and decoding stage and context switch is needless in this design.
