It may be observed as an undesired Miller effect in common-emitter, common-source and " common-cathode " amplifying stages where effective input capacitance is increased.
12.
The gate-drain capacitance is effectively multiplied by the factor 1 + | A _ \ text { v } | \,, thus increasing the total input capacitance and lowering the overall bandwidth.
13.
This causes the PCI's IDSEL signal to reach its active condition more slowly than other PCI bus signals ( due to the RC time constant of both the resistor and the IDSEL pin's input capacitance ).
14.
A better design, called a distributed amplifier, used multiple tubes, but their inputs ( control grids ) were connected along a tapped L-C delay line, so the tubes'input capacitances became part of the delay line.
15.
More modern probe designs use a thick-film electronic circuit in the head that combines the 9 megohm resistor with a fixed-value bypass capacitor; they then place a small adjustable capacitor in parallel with the oscilloscope's input capacitance.
16.
The logical effort of a two-input NAND gate is calculated to be " g " = 4 / 3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3.
17.
The logical effort of a two-input NAND gate is calculated to be " g " = 4 / 3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3.
18.
The path effort is expressed in terms of the "'path logical effort " "'G " ( the product of the individual logical efforts of the gates ), and the "'path electrical effort " "'H " ( the ratio of the load of the path to its input capacitance ).
19.
Ronja however uses a feedbackless design where the PIN has a high working electrical resistance ( 100 kilohms ) which together with the total input capacitance ( roughly 7 pF, 5 pF PIN and 2 pF input MOSFET cascode ) makes the device operate with a passband on a 6 dB / oct slope of low pass formed by PIN working resistance and total input capacitance.
20.
Ronja however uses a feedbackless design where the PIN has a high working electrical resistance ( 100 kilohms ) which together with the total input capacitance ( roughly 7 pF, 5 pF PIN and 2 pF input MOSFET cascode ) makes the device operate with a passband on a 6 dB / oct slope of low pass formed by PIN working resistance and total input capacitance.
