| 11. | This was a synchronous private memory bus which allowed for simultaneous memory input / output transfers.
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| 12. | This bandwidth is what is referred to as the memory bus and can be performance limiting.
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| 13. | Within a year some Sun systems used MBus, another interconnection standard, as a CPU memory bus.
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| 14. | These DIMMs are installed in identical pairs in order to match the width of the memory bus.
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| 15. | DDR3 ECC bits are used to verify the integrity of the data being sent across memory bus.
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| 16. | A bay might contain a processor bus, a shared memory bus, or an I / O bus.
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| 17. | Main memory is directly or indirectly connected to the central processing unit via a " memory bus ".
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| 18. | Each CMIC ASIC is responsible for managing half of the 280-bit memory bus and the 128-bit system bus.
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| 19. | It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.
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| 20. | It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.
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