The 8085 has extensions to support new interrupts, with three maskable vectored interrupts ( RST 7.5, RST 6.5 and RST 5.5 ), one non-maskable interrupt ( TRAP ), and one externally serviced interrupt ( INTR ).
22.
Since a non-maskable interrupt will regain control of the CPU even after executing the instruction sequence DI / HALT, that pair does not represent a true HCF, it will only result in a HCF condition if either the / NMI pin is connected directly to the + 5V rail, making the generation of that signal impossible, or if the interrupt routine that services / NMI ends with a return, placing it back in the HALT state.
23.
The W65C265S consists of a W65C816S ( Static ) Central Processing Unit ( CPU ), 8 kB of Read Only Memory ( ROM ), 576 bytes of Random Access Memory ( RAM ), Processor defined cache under software control, eight 16-bit timers with maskable interrupts, high performance interrupt-driven Parallel Interface Bus ( PIB ), four Universal Asynchronous Receivers and Transmitters ( UART ) with baud rate timers, Monitor " Watch Dog " Timer with " restart " interrupt, twenty-nine priority encoded interrupts, Built-in Emulation features, Time of Day ( ToD ) clock features, Twin Tone Generators ( TGx ), Bus Control Register ( BCR ) for external memory bus control, interface circuitry for peripheral devices, ABORT input for low cost virtual memory interface, and many low power features.
