Examination of the waveform ( e ) during the initial period illustrated, when V in is 0.4 V, shows ( e ) crossing the threshold well before the trigger edge ( positive edge of the clock pulse ) so that there is an appreciable delay before the impulse starts.
32.
A signal from a peripheral device would reset this latch, resuming CPU operation . [ The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal . ])
33.
Then, what about future optical based CPUs that may operate at a terahertz speed, shrinking the maximum signal length to something that won't fit inside the CPU, that is, is there a maximum speed when the size of the CPU cannot be made smaller to accomodate ever-increasing clock pulse speeds ? Preceding talk ) 00 : 33, 5 May 2011 ( UTC)
