As an approximation, it is often useful to discuss the total clock timing uncertainty between two registers as the sum of spatial clock skew ( the spatial differences in clock latency from the clock source ), and clock jitter ( meaning the non-periodicity of the clock at a particular point in the network ).
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Following this lead, the majority of chip-to-chip connection standards underwent an architectural shift from parallel buses to serializer / deserializer ( SERDES ) links called " lanes . " Such serial links eliminate parallel bus clock skew and reduce the number of traces and resultant coupling effects but these advantages come at the cost of a large increase in bit rate on the lanes, and shorter bit periods.
