The IBM System / 360 introduced byte-addressable memory with 8-bit bytes, as opposed to bit-addressable or decimal digit-addressable or word-addressable memory, although its general purpose registers were 32 bits wide, and addresses were contained in the lower 24 bits of those addresses.
32.
For example, POWER8 has up to 8 instruction decoders, but up to 32 register files of 32 general purpose registers each ( 4 read and 4 write port . ), to facilitate simultaneous multithreading, which its instruction cannot be used cross any other register file ( lack of context switch . ).
33.
In this model, four of the processor's eight general purpose registers take on special roles : R4 is used as a base register for loading and storing global data, R5 is used to point to the current function's area on the call stack, and R6 is used as a stack pointer.
34.
The code of the requested SVC was loaded into the Z-80 accumulator, any required parameters were loaded into their specified Z-80 general purpose registers ( or needed regions of RAM set up as required, such as File Control Blocks ), and a Z-80 restart instruction was issued ( RST 40 ).
35.
The Program status word may be stored in one control block ( possibly a PRB, a Program Request Block ), while the general purpose registers may be stored in the immediately preceding control block ( an SVRB, Supervisor Call Request Block, an IRB, Interruption Request Block, or the TCB itself ), depending upon the particular context.
36.
In the System / 360 and early System / 370 architectures, the general purpose registers were 32 bits wide, the machine did 32-bit arithmetic operations, and addresses were always stored in 32-bit words, so the architecture was considered 32-bit, but the machines ignored the top 8 bits of the address resulting in 24-bit addressing.
37.
However it is lacked of integer general purpose register makes it different than its x86 counterpart . ), an 64-bit ALU, a 512?8-bit instruction RAM, a 512?6-bit data RAM, two internal 16-bit buses, a wide instruction word processor, a variable length sequence decoder, a pixel interpolator and an interface supporting a 4 GB linear address space.
