If a programmer stops the program in a debugger, they can observe the contents of these 64 registers ( and a few status registers ) to determine the progress of the machine.
32.
More modern hardware often has one or more interrupt status registers that latch the interrupt requests; well written edge-driven interrupt software often checks such registers to ensure events are not missed.
33.
The hardware interrupt system supports a 4-bit interrupt priority input, which needed to be higher than the priority level stored in the status register ( bits 12-15 ) in order for the interrupt request to be served.
34.
The original ( " flat " ) Commodore 128 used the active low interrupt request line ( / INTR ), which was asserted when the " ready " bit in the 8568's status register changed from 0 to 1.
35.
Like PC-relative addressing, some CPUs have versions of this addressing mode that only refer to one register ( " skip if reg1 = 0 " ) or no registers, implicitly referring to some previously-set bit in the status register.
36.
When set, the interrupt request disable flag ( the bit in the status register ) will disable detection of the signal, but will have no effect on any other interrupts ( however, see below section on the instruction implemented in WDC CMOS processors ).
37.
During an interrupt, the status of the thread currently executing can be preserved ( and later recalled ) by storing the current value of the status register along with the program counter and other active registers into the machine stack or some other reserved area of memory.
38.
All port input and output can therefore be performed by memory move operations on specified addresses in the SFR . Also, different status registers are mapped into the SFR, for use in checking the status of the 8051, and changing some operational parameters of the 8051.
39.
The ALU performs operations such as addition, subtraction, and operations such as AND or OR . Each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation ( zero value, negative number, overflow, or others ).
40.
The detection of a signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector ( & ndash; ) before commencing execution.
