There was also a cheaper version, the " 9200SE ", which had a 20 % lower clock speed and only had a 64-bit memory bus.
42.
The memory controller supported up to 512 MB of synchronous dynamic random access memory ( SDRAM ) and accesses it via a 128-bit memory bus.
43.
Nevertheless, DVFS has been recently proposed for the DDR3 memory bus interface independently by two research groups in 2011 to scale memory power with throughput.
44.
The two models differed in memory subsystem features : the 21071 has a 64-bit memory bus and supports 8 MB to 2 GB of ECC-protected memory.
45.
Because the memory bus voltage and frequency are independent of internal DRAM timings and voltages, scaling this interface should have no effect on memory cell integrity.
46.
The stream processor is usually equipped with a fast, efficient, proprietary memory bus ( crossbar switches are now common, multi-buses have been employed in the past ).
47.
The chipset information also revealed that it uses 256 kilobytes ( KB ) of pipeline burst write-back Level 2 cache with a memory bus speed of 66MHz.
48.
The new chips will be designed for use with the PC 100 memory bus standard being promoted by Intel Corp . of the United States, it said.
49.
Furthermore, David et al . claim their approach improves energy proportionality because the memory bus consumes a lot of static power that is independent of the bus utilization.
50.
Both of these may sap performance and force processors in symmetric multiprocessing ( SMP ) systems to contend for the memory bus, especially if the granularity of the locking is fine.
