The addresses in these registers are linear addresses.
2.
If paging is not enabled, these linear addresses are the same as physical addresses.
3.
The actual location of the beginning of a segment in the linear address space can be calculated with segment?6.
4.
If paging is enabled, the linear addresses are translated into physical addresses by the processor's paging mechanism.
5.
A segment value of 0Ch ( 12 ) would give a linear address at C0h ( 192 ) in the linear address space.
6.
A segment value of 0Ch ( 12 ) would give a linear address at C0h ( 192 ) in the linear address space.
7.
CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task.
8.
Finally, the LDT is actually defined by a descriptor inside the GDT, while the GDT is directly defined by a linear address.
9.
As linear addresses do not necessarily correspond to contiguous physical addresses, this may not be possible in all cases and on all hardware combinations.
10.
Programmers using this feature led to the Gate A20 compatibility issues in later CPU generations, where the linear address space was expanded past 20 bits.
