| 1. | The memory cycle took 12 timing pulses ( 11.72 ?s ).
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| 2. | The AGC memory cycle occurred continuously during AGC operation.
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| 3. | Firmware hubs are allowed to accept firmware memory cycles.
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| 4. | Indirect addressing added 4 memory cycles ( 80 ?s ) for each level of indirection.
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| 5. | Indirect addressing added 3 memory cycles ( 30 �s ) for each level of indirection.
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| 6. | Indexed addressing added 5 memory cycles ( 50 �s ) for each level of indexing.
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| 7. | Basic memory cycle time was 6 microseconds.
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| 8. | Main memory cycle time was 645 ns.
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| 9. | The memory cycle time for a 70 / 15 was 2 microseconds per byte of information.
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| 10. | The calculation of a physical address resulted in no appreciable delay in the effective memory cycle time.
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